Exemplary embodiments of the present invention relate to an integrated circuit, and more particularly, to a delay locked loop of a semiconductor memory device.
Semiconductor memory devices have been continuously improved to increase their integration density and their operating speed. Synchronous memory devices designed to operate in synchronization with clocks provided from the outside of memory chips have been introduced to increase the operating speed of these memory devices. Such memory devices use a delay locked loop (DLL) to generate an internal clock by delaying an external clock for a predetermined time in order that data are outputted in exact synchronization with rising and falling edges of a clock.
A DLL generates an internal clock in which the delay element inside a dynamic random access memory (DRAM) is compensated with respect to an external clock, and this is called a delay locking. The delay locked state refers to a state in which a reference clock (REFCLK) and a feedback clock (FBCLK) are synchronized with each other. A typical DLL achieves the synchronization between a feedback clock (FBCLK) and a reference clock (REFCLK) by adjusting a delay amount.
FIG. 1 is a block diagram of a typical DLL having a closed loop structure.
Referring to FIG. 1, the DLL includes a buffering unit 100, a phase comparison unit 110, a delay control unit 120, a variable delay unit 130, and a delay model unit 140.
The buffering unit 100 is configured to buffer an external clock EXTCLK and transfer the buffered external clock EXTCLK to the inside of the DLL as a reference clock REFCLK. The phase comparison unit 110 is configured to compare a phase of the reference clock REFCLK with a phase of a feedback clock FBCLK, and the delay control unit 120 is configured to generate a delay control signal CTR in response to an output signal of the phase comparison unit 110. The variable delay unit 130 is configured to delay the reference clock REFCLK in response to the delay control signal CTR. The delay model unit 140 is configured to model a delay of an actual clock/data path to an output signal of the variable delay unit 130 and output the feedback signal FBCLK.
The feedback clock FBCLK is a clock in which a delay time of the variable control unit 130 and a delay time of the delay model unit 140 are added to the reference clock REFCLK. The DLL compares the reference clock REFCLK with the feedback clock FBCLK and outputs a desired DLL clock DLLCLK when the two clocks have minimum jitters, that is, a delay locking is achieved.